Carrier For Holding Semiconductor Wafers During A Double-Side Polishing Of The Semiconductor Wafers

ABSTRACT

The invention relates to a carrier for holding semiconductor wafers during a double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing. Some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and an inner or an outer section of a circular path.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to German application DE 10 2009 009497.0 filed Feb. 18, 2009, which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a carrier for holding semiconductor wafersduring double-side polishing of the semiconductor wafers. The inventionalso relates to a method for the double-side polishing of semiconductorwafers in which the carrier is used.

2. Background Art

The production of semiconductor wafers for use as substrates forproducing electronic components regularly comprises at least onedouble-side polishing of the semiconductor wafers, which is carried outin one step and hereinafter is called DSP. During DSP, a semiconductorwafer is situated together with further semiconductor wafers betweenupper and lower rotating polishing plates that are covered withpolishing cloth. Carriers, having cutouts in which the semiconductorwafers lie, guide and hold the semiconductor wafers during polishing.The carriers have on their periphery, an outer toothing by means ofwhich they are rotated as planetary gears of a planetary gear mechanismabout their own axis and the axis of the polishing plates duringpolishing. The semiconductor wafers are polished in the presence ofpolishing agent that is supplied from the upper polishing plate and isdistributed on the polishing cloths. It is necessary to ensure that bothsides of the semiconductor wafer are sufficiently supplied withpolishing agent in order that a uniform polishing material removal isobtained. The sufficient supply of polishing agent is particularlyimportant if polishing is effected by means of a polishing machine ofcompact design. This type of machine accommodates only one carrier,which extends over the entire lower polishing plate, and the polishingplates and the carrier have a common axis of rotation. In this case, alack of polishing agent has the effect that the semiconductor wafer isrestricted in its mobility with regard to the rotation about its ownaxis to an extent such that accumulated frictional heat brings aboutincreased material removal in a partial region of the edge of thesemiconductor wafer and a semiconductor wafer having a wedge-shaped edgesection thus arises. In order to prevent this, EP 1 676 672 A1 proposesimproving the supply of polishing agent to the lower polishing plate byat least 15% of the area of the carrier being occupied by holes thatprovide the polishing agent with a passage to the lower polishing plate.

The inventors of the present invention have determined, however, that aquantitively sufficient supply of polishing agent to the lower polishingplate is admittedly necessary, but does not necessarily counteract allfaults of the edge geometry. This applies in particular to the so-callededge roll-off, which concerns the entire wafer edge and is observedafter DSP. The edge roll-off is described in SEMI standard M69 as asurface deviation in the edge region of semiconductor wafers having alarge diameter. Since more and more area of a semiconductor wafer isbeing qualified for the production of electronic components and the edgeexclusion in present-day extremely high quality semiconductor wafers isonly 1 mm, there is a growing interest in reducing geometry faults inthe edge region. Standardized parameters, for example the ESFQR definedin the SEMI standard, are available for quantitively describing suchgeometry faults.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide means with the aidof which the edge roll-off after DSP can be significantly reduced, and asemiconductor wafer having an advantageous edge geometry becomesavailable. These and other objects are achieved by means of a carrierfor holding semiconductor wafers during double-side polishing of thesemiconductor wafers, comprising cutouts for receiving the semiconductorwafers and passage openings for a polishing agent supplied duringpolishing, wherein some of the passage openings are formed by holeswhich have a diameter of 2 to 8 mm and are arranged on a path which liesat a distance of 1 to 10 mm concentrically around the cutouts and has aninner section, an outer section and two sections between the inner andouter sections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a carrier representing the prior art.

FIG. 2 shows a carrier according to the invention in a first embodiment.

FIG. 3 shows a carrier according to the invention in a secondembodiment.

FIG. 4 shows a carrier according to the invention in a third embodiment.

FIGS. 5 and 6 show the different effect which a carrier according to theinvention has on the edge geometry of a semiconductor wafer after a DSPin comparison with a carrier associated with the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The inventors have discovered that access for the polishing agent to thelower polishing plate, which is situated near to the wafer edge and isarranged at a uniform distance at the wafer edge, makes a significantcontribution to reducing edge roll-off. Therefore, the carrier accordingto the invention has not only the customary passage openings forpolishing agent, but also those which are positioned in accordance withthis insight. It can be used together with others in a polishing machinewith a planetary gear mechanism or by itself in a polishing machine ofcompact design.

The carrier is composed preferably of steel, plastic or ceramic, mostpreferably of hardened steel and is provided, if appropriate, with alow-abrasion and low-friction coating.

The cutouts for receiving semiconductor wafers are lined with plastic inthe customary manner in order to protect the sensitive wafer edge,preferably with inlays having cutouts at regular distances of 5 to 30mm. A particularly preferred form of inlays is described for example inDE 100 18 338 C1.

The passage openings for polishing agent which are arranged away fromthe cutouts can in principle be shaped as desired. Openings having aperiphery in the shape of rounded triangles and quadrangles or ofcircles are preferred. Passage openings such as are described in DE 10247 200 A1 are particularly preferred.

The invention is explained in more detail below with reference tofigures.

The carrier in accordance with FIG. 1, which represents the prior art,comprises cutouts 1 for receiving semiconductor wafers and relativelylarge passage openings 2 for a polishing agent supplied during thepolishing.

The carrier embodied according to the invention in accordance with FIG.2 differs from that shown in FIG. 1 essentially by virtue of a ring ofsmaller passage openings composed of holes 3. The holes have a diameterof 2 to 8 mm and are arranged at a distance of 1 to 10 mm around thecutouts, wherein the distance denotes the shortest distance between thehole edge and the edge of the cutout without taking account of an inlay.The midpoints of the holes lie on a concentric circular path around thecutouts. In accordance with the first embodiment of the carrier, thiscircular path is completely occupied by the holes. Further embodimentsprovide for the holes to form a ring that is open in one section. If thecircular path is regarded as subdivided into four sections having anapproximately identical length, it is possible to differentiate betweenholes 3 a arranged on an inner section, holes 3 b arranged on an outersection, and holes 3 c and 3 d arranged on two central sections lyingbetween the inner and outer sections.

In the case of the carrier in accordance with the second embodiment,which is illustrated in FIG. 3, the holes are not arranged around theentire circumference of the circular path. This is because the inventorshave discovered that occupying the central sections with holes alreadysuffices to obtain a significantly smaller edge roll-off, particularlyif the carrier is used as a planetary gear. The additional arrangementof holes on the inner and/or the outer section primarily increases thestiffness of the carrier. Accordingly, the holes in the case of thecarrier in accordance with the second embodiment are arranged on thecentral sections and additionally on the outer section.

In the case of the carrier in accordance with the third embodiment,which is illustrated in FIG. 4, holes are arranged on the two centralsections and on the inner section of the circular path.

The distance between adjacent holes of a section is 3 to 30 mm and ispreferably always the same, including between two adjacent holes ofadjacent sections.

EXAMPLE

Semiconductor wafers composed of silicon having a diameter of 300 mmwere polished on a DSP machine of the AC2000 type from the manufacturerPeter

Wolters under the same conditions, and the edge roll-off was examined.Carriers in accordance with a first embodiment of the invention wereused in one experiment, and carriers embodied in accordance with theillustration in FIG. 1 were used in a comparative experiment.

FIG. 5 and FIG. 6 show the surface contour of the front side of two ofthe polished semiconductor wafers, plotted as distance A along thediameter D.

In the case of the semiconductor wafer polished according to theinvention, the surface contour of which wafer is illustrated in FIG. 5,virtually no edge roll-off is discernable. By contrast, a semiconductorwafer polished in accordance with the comparative experiment, thesurface contour of the wafer being illustrated in FIG. 6, exhibits apronounced edge roll-off The ESFQR, measured taking account of an edgeexclusion of 1 mm, was particularly low in the case of semiconductorwafers polished according to the invention. Measurements on amultiplicity of semiconductor wafers polished according to the inventionshowed that the ESFQR_(max), that is to say the ESFQR in the sectorshaving the worst edge geometry, varied within the range of 100 to 170nm.

While embodiments of the invention have been illustrated and described,it is not intended that these embodiments illustrate and describe allpossible forms of the invention. Rather, the words used in thespecification are words of description rather than limitation, and it isunderstood that various changes may be made without departing from thespirit and scope of the invention.

1. A carrier for holding semiconductor wafers during double-sidepolishing of the semiconductor wafers, comprising cutouts for receivingthe semiconductor wafers and passage openings for a polishing agentsupplied during the polishing, wherein some of the passage openings areformed by holes which have a diameter of 2 to 8 mm and are arranged at adistance of 1 to 10 mm around the cutouts, wherein the holes arearranged on two central sections and on at least one of an inner or anouter section of a circular path.
 2. The carrier of claim 1, wherein theholes have an identical distance between holes of 3 to 30 mm.
 3. Thecarrier of claim 1, wherein the holes are arranged on the centralsections and additionally on the outer section and the inner section ofthe circular path.
 4. The carrier of claim 2, wherein the holes arearranged on the central sections and additionally on the outer sectionand the inner section of the circular path.
 5. A method for thedouble-side polishing of semiconductor wafers, wherein the semiconductorwafers are held in a carrier of claim 1, during double-side polishing.6. A method for the double-side polishing of semiconductor wafers,wherein the semiconductor wafers are held in a carrier of claim 2,during double-side polishing.
 7. A method for the double-side polishingof semiconductor wafers, wherein the semiconductor wafers are held in acarrier of claim 3, during double-side polishing.
 8. A method for thedouble-side polishing of semiconductor wafers, wherein the semiconductorwafers are held in a carrier of claim 4, during double-side polishing.